State Machine Modeling For HDLs

For efficient code generation from State Machine models into Hardware Description Languages (HDL) such as VHDL, Verilog and Systems C, apply the design practices outlined in this topic.

In an HDL State Machine model, the following are expected:

• Designate Driving Triggers
• Establish Port�Trigger Mapping
• Active State Logic

Designate Driving Triggers

The top level State Machine diagram should be used to model the different modes of a hardware component, and the associated triggers that drive them, as shown in the following diagram.

Asynchronous Triggers

Asynchronous triggers should be modeled according to the following pattern:

1. The trigger should be of type Change (specification: true / false)
2. The active state (Submachine State) should have a transition trigger by it.
3. The target state of the triggered transition should have a self transition with the same trigger

Clock

A trigger of type time, which triggers the transitions to the active state (Submachine State) is deemed as the Clock. The specification of this trigger should be specific to the target language.

Clock Trigger Specifications

Establish Port � Trigger Mapping

After successfully modeling the different operating modes of the component, and the triggers associated with them, you must associate the triggers with the component's ports as shown in the following diagram.

A Dependency relationship from the Port to the associated trigger should be used to signify their association.

See Also:

• State Machine Diagram
• Transition
• SW Code Generation - State Machine Diagrams.

Active State Logic

The first two aspects, above, put in place the preliminaries required for efficient interpretation of the hardware components. The actual State Machine logic is now modeled within the Active (Submachine) state.