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State Machine Modeling For HDLs
For efficient code generation from State Machine models into Hardware Description Languages (HDL) such as VHDL, Verilog and SystemC, apply these design practices.
In an HDL State Machine model, the following are expected:
· | Designate Driving Triggers |
· | Establish Port�Trigger Mapping |
· | Active State Logic |
How to
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Designate Driving Triggers |
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Establish Port-Trigger Mapping |
After successfully modeling the different operating modes of the component, and the triggers associated with them, you must associate the triggers with the component's ports A Dependency relationship from the Port to the associated trigger is used to signify their association
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Active State Logic |
The first two aspects, above, put in place the preliminaries required for efficient interpretation of the hardware components. The actual State Machine logic is now modeled within the Active (Submachine) state.
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Notes
· | To be able to generate code from behavioral models, all behavioral constructs should be contained within a Class |
· | The current code generation engine supports only one clock trigger for a component |
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