Please note : This help page is not for the latest version of Enterprise Architect. The latest help can be found here.
Verilog Conventions
Enterprise Architect supports round-trip engineering of Verilog, where the following conventions are used.
Stereotypes
Stereotype |
Applies To |
Corresponds To |
|---|---|---|
asynchronous |
Method |
A concurrent process.
|
enumeration |
Inner Class |
An enum type.
|
initializer |
Method |
An initializer process.
|
module |
Class |
A module.
|
part |
Attribute |
A component instantiation.
|
port |
Attribute |
A port.
|
synchronous |
Method |
A sequential process.
|
Tagged Values
Tag |
Applies To |
Corresponds To |
|---|---|---|
kind |
Attribute (signal) |
The signal kind (such as register, bus).
|
mode |
Attribute (port) |
The port mode (in, out, inout).
|
Portmap |
Attribute (part) |
The generic / port map of the component instantiated.
|
sensitivity |
Method |
The sensitivity list of a sequential process.
|
type |
Attribute |
The range or type value of an attribute.
|
Verilog Toolbox Pages
Access Diagram | Diagram Toolbox: More tools | HDL | Verilog Constructs
Drag these icons onto a diagram to model a Verilog design.
Page |
Item |
Action |
||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Verilog |
Module |
Defines a Verilog Module. A module-stereotyped Class element.
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Enumeration |
Defines an Enumerated Type. An enumeration element.
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Verilog Features |
Port |
Defines a Verilog Port. A port-stereotyped attribute.
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Part |
Defines a Verilog component instantiation. A part-stereotyped attribute.
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Attribute |
Defines an attribute.
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Procedure
|
Defines a Verilog process:
|
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