Please note : This help page is not for the latest version of Enterprise Architect. The latest help can be found here.
VHDL Conventions
Enterprise Architect supports round-trip engineering of VHDL, where the following conventions are used.
Stereotypes
Stereotype |
Applies To |
Corresponds To |
---|---|---|
architecture |
Class |
An architecture.
|
asynchronous |
Method |
An asynchronous process.
|
configuration |
Method |
A configuration.
|
enumeration |
Inner Class |
An enum type.
|
entity |
Interface |
An entity.
|
part |
Attribute |
A component instantiation.
|
port |
Attribute |
A port.
|
signal |
Attribute |
A signal declaration.
|
struct |
Inner Class |
A record definition.
|
synchronous |
Method |
A synchronous process.
|
typedef |
Inner Class |
A type or subtype definition.
|
Tagged Values
Tag |
Applies To |
Corresponds To |
---|---|---|
isGeneric |
Attribute (port) |
The port declaration in a generic interface.
|
isSubType |
Inner Class (typedef) |
A subtype definition.
|
kind |
Attribute (signal) |
The signal kind (such as register, bus).
|
mode |
Attribute (port) |
The port mode (in, out, inout, buffer, linkage).
|
portmap |
Attribute (part) |
The generic / port map of the component instantiated.
|
sensitivity |
Method (synchronous) |
The sensitivity list of a synchronous process.
|
type |
Inner Class (typedef) |
The type indication of a type declaration.
|
typeNameSpace |
Attribute (part) |
The type namespace of the instantiated component.
|
VHDL Toolbox Pages
Access Diagram | Diagram Toolbox: More tools | HDL | VHDL Constructs
Drag these icons onto a diagram to model a VHDL design.
Page |
Item |
Action |
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VHDL |
Architecture |
Defines an architecture to be associated with a VHDL entity. An architecture-stereotyped Class element.
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Entity |
Defines a VHDL entity to contain the Port definitions. An entity-stereotyped interface element.
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Enumeration |
Defines an Enumerated Type. An Enumeration element.
|
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Struct |
Defines a VHDL record. A struct-stereotyped Class element.
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Typedef |
Defines a VHDL type or subtype. A typedef-stereotyped Class element.
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VHDL Features |
Port |
Defines a VHDL Port. A port-stereotyped attribute.
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Part |
Defines a VHDL component instantiation. A part-stereotyped attribute.
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Signal |
Defines a VHDL signal. A signal-stereotyped attribute.
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Procedure
|
Defines a VHDL process:
|
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