VHDL Source Code Engineering fault

[AlexB.]

Hi,

I modeled a state machine (SM) in EA. After compiling it to VHDL, I was able to test the vhdl code successful with ModelSim and a self written testbench.  

Now i made another SM, but after compiling the SM, there is missing everything after the signal declaration in the vhdl file.
I don't know what I did different this time...
Maybe someone knows what i did wrong?  

Also, I'm not pretty sure if I use the right states, operation declarations, transitions, StateMachine blocks and so on... is there a tutorial about creating EA SM for vhdl code? I haven't found anything useful.

Thanks in advance,
Alex