Is a virtual bus connection best represente with full ports?

[mse]

I am modeling an AUTOSAR system (RTE communication), but this can apply to any other system. Suppose you have two blocks that send data to one another. There is a connector between the two blocks. However, the connector represents a more complicated infrastructure and has its own design etc. The two blocks to not send messages to one another, instead they read and write (like in shared memory, or some blackboard type communication) to another block.

In the scenario above, the RTE, or that "shared memory" or "blackboard", is actually a <<fullport>> because it has its own structure and actually handles the reading and writing of data, the blocks communicate with one another via that repository.

On the other hand, if I say <<fullport>> that means that my blocks actually have a part which handles the communication, but that is not true. In that sense it should be <<proxyport>> linked by an association block representing the shared memory, blackboard or whatever mechanism is used.