VHDL documentation

[Martin S.]

Hello,

I'm trying to use Enterprise Architect for VHDL modelling. Unfortunately the documentation in the help file is very sparse. Here are the questions I have so far:

-Why should I use ports for entities? I can also use attributes for input and output ports. When I use attributes I don't need to define any supporting elements.

-How can I define a std_logic_vector with downto notation?:

Code: [Select]

 signal example : std_logic_vector (23 downto 0);
-How can I define a subtype:

Code: [Select]

 subtype small_int is integer range -128 to 127;
Is there a way to attach Project files to forum posts? I think it would be easier for you to understand what I was doing if you could have a look at my testing project.