Hide Stereotype for SysML 1.3 Ports

[philchudley]

Hi All

SysML 1.3 introduced the concept of <<full>> and <<proxy>> ports

Naturally, these stereotypes appear on Block Definition Diagrams along with other stereotypes like <<block>> and <<interfaceBlock>>

This is fine, but with a large number of ports, particularly if ports are nested, the presence of stereotypes on Ports clutters  the diagram very quickly

Using Diagram Properties it is possible to turn off Element stereotypes, which works for <<blocks>> and <<interfaceBlock>> but NOT for Ports  

These stereotypes are still present

Is this a bug that needs reporting, a feature, or is there a way to hide the stereotype on a Port?

My work around (at the moment and SysML purists stop reading now) which is not really valid SysML but works in EA, is to use a non stereotyped Port regardless of whether it is a <<full>> or a <<proxy>>

Another gripe, element alignment DOES NOT WORK ON PORTS   really annoying when trying to align Ports

Cheers
Phil

[natvig]

I think I have already sent a bug report about hiding port stereotypes. However, I think you should send another one, to put some more pressure on Sparx.

Omitting the stereotypes on SysML ports is fine, and perfectly valid SysML. However, it is not valid SysML to use the full stereotype on a port that is typed by an interface block, or to use the proxy stereotype on a port that is typed by a block. The type of a non-stereotyped port can be implicitly determined by the port type (block or interface blocks).

I agree, it is annoying that alignment of ports is not working.

(Another bug wrt SysML ports, is that multiplicity information is not displayed when ports are stereotyped either full or proxy. I have filed a bug report on this which has been accepted by Sparx.)

/Hans

[avi10000]

Has this been fixed?